The present disclosure relates to a resistance-change memory device in which a memory element whose resistance value is changed in accordance with an applied voltage is connected between a bit line and either a source line or a voltage supplying layer called a plate, and relates to a method of operating the same.
A resistance-change memory device is known which has a memory element whose resistance value is changed either by implanting conductive ions into an insulating film or by drawing out conductive ions from an insulating film every memory cell. The resistance-change memory device, for example, is disclosed in Non-Patent Document of K. Aratani, K. Ohba, T. Mizuguchi, S. Yasuda, T. Shiimoto, T. Tsushima, T. Sone, K. Endo, A. Kouchiyama, S. Sasaki, A. Maesaka, N. Yamada, and H. Narisawa: “A Novel Resistance Memory with High Scalability and Nanosecond Switching,” Technical Digest IEDM 2007, pp. 783 to 786.
The memory element has a lamination structure in which the layer, described above, for supplying the conductive ions and insulating films are formed between two electrodes. A memory cell is configured in such a way that the memory element and an access transistor is connected in series between the bit line and the plate so as to enable active matrix driving to be carried out.
Such a memory cell is a sort of memory utilizing a 1T1R type current drive system because it includes one transistor (T) and one (variable) resistor (R). The memory using the conductive ions is generally called a ReRAM together with a memory using oxidation and reduction of an insulating layer.
In the ReRAM, small and large of the resistance value are made to correspond to write and erasure of data, respectively, and a writing operation and an erasing operation can be carried out by using a pulse having a short duration on the order of nanoseconds. For this reason, the ReRAM gets a lot of attention as a non-volatile memory (NVM) which can carry out a high-speed operation like a random access memory (RAM).
FIG. 1 shows a diagram of correlation between a conductance and a current in a low-resistance state of the ReRAM using conductive ions.
An axis of abscissa in FIG. 1 represents a reciprocal number (conductance) of a resistance value RLRS in a low-resistance state (LRS). In addition, an axis of ordinate in FIG. 1 represents a value of a set current (Iset) in a resistance decreasing operation (referred to as “a set operation” in this case).
As apparent from FIG. 1, the resistance value of the memory element is approximately, linearly changed in accordance with the set current. Such characteristics can be realized similarly even in any other suitable resistance-change memory such as the ReRAM.
From the foregoing, the ReRAM has an advantage that the current control is precisely carried out, thereby narrowing a resistance value distribution, or a multi-valued memory can be realized.
However, the ReRAM also has a disadvantage that when the precision of the current control is low, a desired resistance value is hard to obtain and especially, excessive current application results in that a resistance increasing (reset) operation is hard to carry out, or repetitive characteristics are reduced.
A system for regulating an element current in accordance with gate electric potential control (word line control) of an access transistor, and a system for controlling a current of a bit line are known as a system for carrying out the control for the element current.
In particular, since the word line is made of a gate metal and thus includes a large number of gate capacitances as parasitic capacitances, the word line is hard to control because of a large wiring capacitance thereof. Therefore, high-speed driving is difficult for the word line. In addition, when a high-speed operation is attempted to be carried out, since it is necessary to increase a driving force of a control circuit for the word line, it is feared to cause an increase in cost due to an increase in a circuit area.
On the other hand, since the bit line is composed of an upper layer wiring layer and has a relatively small wiring capacitance, the bit line is easy to control. Therefore, the high-speed operation can be carried out with the current control system using the bit line. In addition, with the current control for the bit line, it is possible to suppress the circuit area and it is possible to save the cost from this viewpoint. Therefore, the adoption of the current control system for the bit line results in that the cost saving and the high-speed operation can be made compatible with each other.
With the system for regulating the element current in accordance with the current control for the bit line, in addition to the bit lines and the word lines, source lines also need to be separated in a row direction, thereby enabling the electric potential driving to be carried out. In that context, the system (or the access system) to which the current control method concerned is applied is called a three-wire system.
With regard to the current control for the bit line based on the three-wire system, the inventor of this application previously made several proposals. One of the techniques disclosed in such proposals, for example, is described in Japanese Patent Laid-Open No. 2010-170617. In addition, an example in which the current control system is applied to a resistance-change memory utilizing a spin implantation system, for example, is disclosed in domestic re-publication of PCT international publication for patent application WO2007/015358.
It is noted that a resistance memory disclosed in Non-Patent Document 1 has an array structure in which for processing easiness, an upper electrode is processed into a plate-like shape, a drain of an access transistor is used as a memory node, and a source is connected to a bit line processed into a line-like shape. This array structure adopts a system (two-wire system) in which one memory cell is selected by two wires of the bit line and the word line.